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1 p/n:pm1219 rev. 1.3, dec. 09, 2005 kh29lv400c t/b 4m-bit [512k x 8 / 256k x 16] cmos single voltage 3v only flash memory ? ready/busy# pin (ry/by#) - provides a hardware method of detecting program or erase operation completion sector protection - hardware method to disable any combination of sectors from program or erase operations - temporary sector unprotect allows code changes in previously locked sectors cfi (common flash interface) compliant - flash device parameters stored on the device and provide the host system to access 100,000 minimum erase/program cycles latch-up protected to 100ma from -1v to vcc+1v boot sector architecture - t = top boot sector - b = bottom boot sector package type: - 48-pin tsop - all pb-free devices are rohs compliant compatibility with jedec standard - pinout and software compatible with single-power supply flash 20 years data retention features extended single - supply voltage range 2.7v to 3.6v 524,288 x 8/262,144 x 16 switchable single power supply operation - 3.0v only operation for read, erase and program operation fast access time: 70/90ns low power consumption - 30ma maximum active current - 0.2ua typical standby current command register architecture - byte/word programming (9us/11us typical) - sector erase (sector structure 16k-byte x 1, 8k-byte x 2, 32k-byte x1, and 64k-byte x7) auto erase (chip & sector) and auto program - automatically erase any combination of sectors with erase suspend capability. - automatically program and verify data at specified address erase suspend/erase resume - suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase. status reply - data# polling & toggle bit for detection of program and erase operation completion general description the kh29lv400c t/b is a 4-mega bit flash memory organized as 512k bytes of 8 bits or 256k words of 16 bits. mxic's flash memories offer the most cost-effec- tive and reliable read/write non-volatile random access memory. the kh29lv400c t/b is packaged in 44-pin sop, 48-pin tsop and 48-ball csp. it is designed to be reprogrammed and erased in system or in standard eprom programmers. the standard kh29lv400c t/b offers access time as fast as 55ns, allowing operation of high-speed micropro- cessors without wait states. to eliminate bus conten- tion, the kh29lv400c t/b has separate chip enable (ce#) and output enable (oe#) controls. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the kh29lv400c t/b uses a command register to manage this functionality. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming, while maintaining maxi- mum eprom compatibility. mxic flash technology reliably stores memory contents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy- cling. the kh29lv400c t/b uses a 2.7v~3.6v vcc supply to perform the high reliability erase and auto program/erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v.
2 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 pin configurations pin description symbol pin name a0~a17 address input q0~q14 data input/output q15/a-1 q15 (word mode)/lsb addr(byte mode) ce# chip enable input we# write enable input byte# word/byte selection input reset# hardware reset pin/sector protect unlock oe# output enable input ry/by# ready/busy output vcc power supply pin (2.7v~3.6v) gnd ground pin 48 tsop (standard type) (12mm x 20mm) a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# reset# nc nc ry/by# nc a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 byte# gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc q11 q3 q10 q2 q9 q1 q8 q0 oe# gnd ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 kh29lv400c t/b
3 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 block structure table 1: kh29lv400ct sector architecture note: byte mode:address range a17:a-1, word mode:address range a17:a0. sector sector size address range sector address byte mode word mode byte mode (x8) word mode (x16) a17 a16 a15 a14 a13 a12 sa0 64kbytes 32kwords 00000-0ffff 00000-07fff 0 0 0 x x x sa1 64kbytes 32kwords 10000-1ffff 08000-0ffff 0 0 1 x x x sa2 64kbytes 32kwords 20000-2ffff 10000-17fff 0 1 0 x x x sa3 64kbytes 32kwords 30000-3ffff 18000-1ffff 0 1 1 x x x sa4 64kbytes 32kwords 40000-4ffff 20000-27fff 1 0 0 x x x sa5 64kbytes 32kwords 50000-5ffff 28000-2ffff 1 0 1 x x x sa6 64kbytes 32kwords 60000-6ffff 30000-37fff 1 1 0 x x x sa7 32kbytes 16kwords 70000-77fff 38000-3bfff 1 1 1 0 x x sa8 8kbytes 4kwords 78000-79fff 3c000-3cfff 1 11100 sa9 8kbytes 4kwords 7a000-7bfff 3d000-3dfff 1 11101 sa10 16kbytes 8kwords 7c000-7ffff 3e000-3ffff 1 1111x sector sector size address range sector address byte mode word mode byte mode (x8) word mode (x16) a17 a16 a15 a14 a13 a12 sa0 16kbytes 8kwords 00000-03fff 00000-01fff 0 0000x sa1 8kbytes 4kwords 04000-05fff 02000-02fff 0 00010 sa2 8kbytes 4kwords 06000-07fff 03000-03fff 0 00011 sa3 32kbytes 16kwords 08000-0ffff 04000-07fff 0 0 0 1 x x sa4 64kbytes 32kwords 10000-1ffff 08000-0ffff 0 0 1 x x x sa5 64kbytes 32kwords 20000-2ffff 10000-17fff 0 1 0 x x x sa6 64kbytes 32kwords 30000-3ffff 18000-1ffff 0 1 1 x x x sa7 64kbytes 32kwords 40000-4ffff 20000-27fff 1 0 0 x x x sa8 64kbytes 32kwords 50000-5ffff 28000-2ffff 1 0 1 x x x sa9 64kbytes 32kwords 60000-6ffff 30000-37fff 1 1 0 x x x sa10 64kbytes 32kwords 70000-7ffff 38000-3ffff 1 1 1 x x x table 2: KH29LV400CB sector architecture note: byte mode:address range a17:a-1, word mode:address range a17:a0.
4 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15/a-1 a0-a17 ce# oe# we# reset#
5 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 automatic programming the kh29lv400c t/b is byte programmable using the automatic programming algorithm. the automatic pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. the typical chip programming time at room temperature of the kh29lv400c t/b is less than 10 sec- onds. automatic chip erase the entire chip is bulk erased using 10 ms erase pulses according to mxic's automatic chip erase algorithm. typical erasure at room temperature is accomplished in less than 4 second. the automatic erase algorithm au- tomatically programs the entire array prior to electrical erase. the timing and verification of electrical erase are controlled internally within the device. automatic sector erase the kh29lv400c t/b is sector(s) erasable using mxic's auto sector erase algorithm. the automatic sector erase algorithm automatically programs the specified sector(s) prior to electrical erase. the timing and verifi- cation of electrical erase are controlled internally within the device. an erase operation can erase one sector, multiple sectors, or the entire device. automatic programming algorithm mxic's automatic programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and a0h) and a program command (program data and address). the device automatically times the programming pulse width, provides the pro- gram verification, and counts the number of sequences. a status bit similar to data# polling and a status bit toggling between consecutive read cycles, provide feed- back to the user as to the status of the programming operation. refer to write operation status, table7, for more information on these status bits. automatic erase algorithm mxic's automatic erase algorithm requires the user to write commands to the command register using stan- dard microprocessor write timings. the device will auto- matically pre-program and verify the entire array. then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. a status bit toggling between consecu- tive read cycles provides feedback to the user as to the status of the erasing operation. register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. during write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. during a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of we# or ce#, whichever happens first. mxic's flash technology combines years of eprom experience to produce the highest levels of quality, reli- ability, and cost effectiveness. the kh29lv400c t/b electrically erases all bits simultaneously using fowler- nordheim tunneling. the bytes are programmed by us- ing the eprom programming mechanism of hot elec- tron injection. during a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. during a sector erase cycle, the command register will only respond to erase suspend command. after erase suspend is completed, the device stays in read mode. after the state machine has completed its task, it will allow the command regis- ter to respond to its full command set. automatic select the automatic select mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on q7~q0. this mode is mainly adapted for programming equipment on the de- vice to be programmed with its programming algorithm. when programming by high voltage method, automatic select mode requires vid (11.5v to 12.5v) on address pin a9 and other address pin a6, a1 as referring to table 3. in addition, to access the automatic select codes in- system, the host can issue the automatic select com- mand through the command register without requiring vid, as shown in table4. to verify whether or not sector being protected, the sec- tor address must appear on the appropriate highest order
6 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 address bit (see table 1 and table 2). the rest of address bits, as shown in table3, are don't care. once all neces- sary bits have been set as required, the programming equipment may read the corresponding identifier code on q7~q0. table 3. kh29lv400c t/b auto select mode operation note:sa=sector address, x=don't care, l=logic low, h=logic high a17 a11 a8 a5 description mode ce# oe# we# re- | | a9 | a6 | a1 a0 q15~q0 set# a12 a10 a7 a2 manufacture l l h h x x vid x l x l l c2h code read device id word l l h h x x vid x l x l h 22b9h silicon (top boot block) byte l l h h x x vid x l x l h xxb9h id device id (bottom word l l h h x x vid x l x l h 22bah boot block) byte l l h h x x vid x l x l h xxbah xx01h sector protection l l h h sa x vid x l x h l (protected) verification xx00h (unprotected)
7 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycle addr data addr data addr data addr data addr data addr data reset 1 xxxh f0h read 1 ra rd read silicon id word 4 555h aah 2aah 55h 555h 90h adi ddi byte 4 aaah aah 555h 55h aaah 90h adi ddi sector protect word 4 555h aah 2aah 55h 555h 90h (sa) xx00h verify x02h xx01h byte 4 aaah aah 555h 55h aaah 90h (sa) 00h x04h 01h program word 4 555h aah 2aah 55h 555h a0h pa pd byte 4 aaah aah 555h 55h aaah a0h pa pd chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h aaah 10h sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h sa 30h sector erase suspend 1 xxxh b0h sector erase resume 1 xxxh 30h table 4. kh29lv400c t/b command definitions note: 1. adi = address of device identifier; a1=0, a0 = 0 for manufacturer code,a1=0, a0 = 1 for device code. a2-a17=do not care. (refer to table 3) ddi = data of device identifier : c2h for manufacture code, b9h/bah (x8) and 22b9h/22bah (x16) for device code. x = x can be vil or vih ra=address of memory location to be read. rd=data to be read at location ra. 2. pa = address of memory location to be programmed. pd = data to be programmed at location pa. sa = address of the sector to be erased. 3. the system should generate the following address patterns: 555h or 2aah to address a10~a0 in word mode/aaah or 555h to address a10~a-1 in byte mode. address bit a11~a17=x=don't care for all address commands except for program address (pa) and sector address (sa). write sequence may be initiated with a11~a17 in either state. 4. for sector protect verify operation: if read out data is 01h, it means the sector has been protected. if read out data is 00 h, it means the sector is still not being protected.
8 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 address q8~q15 description ce# oe# we# re- a17 a10 a9 a8 a6 a5 a1 a0 q0~q7 byte byte set# a11 a7 a2 =vih =vil read l l h h ain dout dout q8~q14=high z q15=a-1 write l h l h ain din(3) din q8~q14=high z q15=a-1 reset x x x l x high z high z high z temporary sector unlock x x x vid ain din din high z output disable l h h h x high z high z high z standby vcc x x vcc x high z high z high z 0.3v 0.3v sector protect l h l vid sa x x x l x h l din x x chip unprotect l h l vid x x x x h x h l din x x sector protection verify l l h h sa x vid x l x h l code(5) x x table 5. kh29lv400c t/b bus operation notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 4. 2. vid is the silicon-id-read high voltage, 11.5v to 12.5v. 3. refer to table 4 for valid data-in during a write operation. 4. x can be vil or vih. 5. code=00h/xx00h means unprotected. code=01h/xx01h means protected. 6. a17~a12=sector address for sector protect. 7. the sector protect and chip unprotect functions may also be implemented via programming equipment. sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. command definitions device operations are selected by writing specific ad- dress and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 4 defines the valid register command
9 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to vil. ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at vih. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. write commands/command sequences to program data to the device or erase sectors of memory , the system must drive we# and ce# to vil, and oe# to vih. an erase operation can erase one sector, multiple sectors , or the entire device. table indicates the address space that each sector occupies. a "sector address" consists of the address bits required to uniquely select a sector. the "writing specific address and data commands or sequences into the command register initiates device operations. table 1 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on q7-q0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence section for more information. icc2 in the dc characteristics table represents the active current specification for the write mode. the "ac characteristics" section contains timing specification table and timing diagrams for write operations. standby mode when using both pins of ce# and reset#, the device enter cmos standby with both pins held at vcc 0.3v. if ce# and reset# are held at vih, but not within the range of vcc 0.3v, the device will still be in the standby mode, but the standby current will be larger. during auto algorithm operation, vcc active current (icc2) is required even ce# = "h" until the operation is completed. the device can be read with standard access time (tce) from either of these standby modes, before it is ready to read data. output disable with the oe# input at a logic high level (vih), output from the devices are disabled. this will cause the output pins to be in a high impedance state. reset# operation the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of trp, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity current is reduced for the duration of the reset# pulse. when reset# is held at vss 0.3v, the device draws cmos standby current (icc4). if reset# is held at vil but not within vss 0.3v, the standby current will be greater. the reset# pin may be tied to system reset circuitry. a system reset would that also reset the flash memory, enabling the system to read the boot-up firm-ware from the flash memory. if reset# is asserted during a program or erase operation, the ry/by# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a
10 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 program or erase operation is completed within a time of tready (not during embedded algorithms). the system can read data trh after the reset# pin returns to vih. refer to the ac characteristics tables for reset# parameters and to figure 24 for the timing diagram. read/reset command the read or reset operation is initiated by writing the read/ reset command sequence into the command register. microprocessor read cycles retrieve array data. the de- vice remains enabled for reads until the command regis- ter contents are altered. if program-fail or erase-fail happen, the write of f0h will reset the device to abort the operation. a valid com- mand must then be written to place the device in the desired state. silicon-id read command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manu- facturer and device codes must be accessible while the device resides in the target system. prom program- mers typically access signature codes by raising a9 to a high voltage (vid). however, multiplexing high voltage onto address lines is not generally desired system de- sign practice. the kh29lv400c t/b contains a silicon-id-read opera- tion to supple traditional prom programming methodol- ogy. the operation is initiated by writing the read silicon id command sequence into the command register. fol- lowing the command write, a read cycle with a1=vil, a0=vil retrieves the manufacturer code of c2h/00c2h. a read cycle with a1=vil, a0=vih returns the device code of b9h/22b9h for kh29lv400ct, bah/22bah for KH29LV400CB. set-up automatic chip/sector erase commands chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cycles are then followed by the chip erase command 10h or sector erase command 30h. the automatic chip erase does not require the device to be entirely pre-programmed prior to executing the auto- matic chip erase. upon executing the automatic chip erase, the device will automatically program and verify the entire memory for an all-zero data pattern. when the device is automatically verified to contain an all-zero pat- tern, a self-timed chip erase and verify begin. the erase and verify operations are completed when the data on q7 is "1" at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). if the erase operation was unsuccessful, the data on q5 is "1"(see table 7), indicating the erase operation ex- ceed internal timing limit. the automatic erase begins on the rising edge of the last we# or ce# pulse, whichever happens first in the com- mand sequence and terminates when the data on q7 is "1" at which time the device returns to the read mode, or the data on q6 stops toggling for two consecutive read cycles at which time the device returns to the read mode.
11 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 pins a0 a1 q15~q8 q7 q6 q5 q4 q3 q2 q1 q0 code(hex) manufacture code word vil vil 00h 1 1 0 0 0 0 1 0 00c2h byte vil vil x 1 1 0 0 0 0 1 0 c2h device code word vih vil 22h 1 0 1 1 1 0 0 1 22b9h for kh29lv400ct byte vih vil x 1 0 1 1 1 0 0 1 b9h device code word vih vil 22h 1 0 1 1 1 0 1 0 22bah for KH29LV400CB byte vih vil x 1 0 1 1 1 0 1 0 bah sector protection x vih x 0 0 0 0 0 0 0 1 01h (protected) verification x vih x 0 0 0 0 0 0 0 0 00h (unprotected) table 6. expanded silicon id code reading array data the device is automatically set to reading array data after device power-up. no commands are required to re- trieve data. the device is also ready to read array data after completing an automatic program or automatic erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the sys- tem can read array data using the standard read tim- ings, except that if it reads at an address within erase- suspended sectors, the device outputs status data. af- ter completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume co mmands ? for more infor-mation on this mode. the system must issue the reset command to re-en- able the device for reading array data if q5 goes high, or while in the autoselect mode. see the "reset command" section, next. reset command writing the reset command to the device resets the de- vice to reading array data. address bits are don't care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence be-fore programming begins. this resets the device to reading array data (also applies to programming in erase sus- pend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an silicon id read command se- quence. once in the silicon id read mode, the reset command must be written to return to reading array data (also applies to silicon id read during erase sus- pend). if q5 goes high during a program or erase operation, writ- ing the reset command returns the device to read-ing array data (also applies during erase suspend).
12 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 erase margin has been achieved for the memory array (no erase verification command is required). sector erase is a six-bus cycle operation. there are two "un- lock" write cycles. these are followed by writing the set- up command 80h. two more "unlock" write cycles are then followed by the sector erase command 30h. the sector address is latched on the falling edge of we# or ce#, whichever happens later, while the command (data) is latched on the rising edge of we# or ce#, whichever happens first. sector addresses selected are loaded into internal register on the sixth falling edge of we# or ce#, whichever happens later. each successive sector load cycle started by the falling edge of we# or ce#, whichever happens later must begin within 50us from the rising edge of the preceding we# or ce#, whichever happens first. otherwise, the loading period ends and internal auto sector erase cycle starts. (monitor q3 to determine if the sector erase timer window is still open, see section q3, sector erase timer.) any command other than sector erase(30h) or erase suspend(b0h) during the time-out period resets the device to read mode. sector erase commands the automatic sector erase does not require the de- vice to be entirely pre-programmed prior to executing the automatic sector erase set-up command and au- tomatic sector erase command. upon executing the automatic sector erase command, the device will auto- matically program and verify the sector(s) memory for an all-zero data pattern. the system is not required to provide any control or timing during these operations. when the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. the erase and verify operations are complete when either the data on q7 is "1" at which time the de- vice returns to the read mode, or the data on q6 stops toggling for two consecutive read cycles at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic sector erase algorithm, note that the erase automatically terminates when adequate status q7 q6 q5 q3 q2 ry/ (note1) (note2) by# byte program in auto program algorithm q7# toggle 0 n/a no 0 toggle auto erase algorithm 0 toggle 0 1 toggle 0 erase suspend read 1 no 0 n/a toggle 1 (erase suspended sector) toggle in progress erase suspended mode erase suspend read data data data data data 1 (non-erase suspended sector) erase suspend program q7# toggle 0 n/a n/a 0 byte program in auto program algorithm q7# toggle 1 n/a no 0 toggle exceeded time limits auto erase algorithm 0 toggle 1 1 toggle 0 erase suspend program q7# toggle 1 n/a n/a 0 table 7. write operation status note: 1. q7 and q2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. q5 switches to '1' when an auto program or auto erase operation has exceeded the maximum timing limits. see "q5:exceeded timing limits " for more information.
13 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 erase suspend this command only has meaning while the state ma- chine is executing automatic sector erase operation, and therefore will only be responded during automatic sector erase operation. when the erase suspend com- mand is written during a sector erase operation, the de- vice requires a maximum of 20us to suspend the erase operations. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after this command has been ex- ecuted, the command register will initiate erase suspend mode. the state machine will return to read mode auto- matically after suspend is ready. at this time, state ma- chine only allows the command register to respond to the read memory array, erase resume and program commands. the system can determine the status of the program operation using the q7 or q6 status bits, just as in the standard program operation. after an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended sectors. erase resume this command will cause the command register to clear the suspend state and return back to sector erase mode but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions. another erase suspend command can be written after the chip has resumed erasing. however, a 10ms time delay must be required after the erase re- sume command, if the system implements an endless erase suspend/resume loop, or the number of erase sus- pend/resume is exceeded 1024 times. the erase times will be expended if the erase behavior always be sus- pended. (please refer to mxic flash application note for details.) automatic program commands to initiate automatic program mode, a three-cycle com- mand sequence is required. there are two "unlock" write cycles. these are followed by writing the automatic pro- gram command a0h. once the automatic program command is initiated, the next we# pulse causes a transition to an active pro- gramming operation. addresses are latched on the fall- ing edge, and data are internally latched on the rising edge of the we# or ce#, whichever happens first. the rising edge of we# or ce#, whichever happens first, also begins the programming operation. the system is not required to provide further controls or timings. the device will automatically provide an adequate internally generated program pulse and verify margin. the device provides q2, q3, q5, q6, q7, and ry/by# to determine the status of a write operation. if the pro- gram operation was unsuccessful, the data on q5 is "1"(see table 7), indicating the program operation exceed internal timing limit. the automatic programming opera- tion is completed when the data read on q6 stops tog- gling for two consecutive read cycles and the data on q7 and q6 are equivalent to data written to these two bits, at which time the device returns to the read mode (no program verify command is required). word/byte program command sequence the device programs one byte of data for each program operation. the command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically generates the program pulses and verifies the programmed cell margin. table 1 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using q7, q6, or ry/by#. see "write operation status" for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the byte program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a "0" back to a "1". attempting to do so may halt the operation and set q5 to "1", or cause the data# polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is
14 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 still "0". only erase operations can convert a "0" to a "1". write operation status the device provides several bits to determine the sta- tus of a write operation: q2, q3, q5, q6, q7, and ry/ by#. table 10 and the following subsections describe the functions of these bits. q7, ry/by#, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. q7: data# polling the data# polling bit, q7, indicates to the host sys-tem whether an automatic algorithm is in progress or com- pleted, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the automatic program algorithm, the device out- puts on q7 the complement of the datum programmed to q7. this q7 status also applies to programming dur- ing erase suspend. when the automatic program algo- rithm is complete, the device outputs the datum pro- grammed to q7. the system must provide the program address to read valid status information on q7. if a pro- gram address falls within a protected sector, data# poll- ing on q7 is active for approximately 1 us, then the de- vice returns to reading array data. during the automatic erase algorithm, data# polling pro- duces a "0" on q7. when the automatic erase algo- rithm is complete, or if the device enters the erase sus- pend mode, data# polling produces a "1" on q7. this is analogous to the complement/true datum output de- scribed for the automatic program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement," or "0". the system must provide an address within any of the sec- tors selected for erasure to read valid status information on q7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on q7 is active for approximately 100 us, then the device returns to reading array data. if not all selected sectors are protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects q7 has changed from the complement to true data, it can read valid data at q7-q0 on the following read cycles. this is because q7 may change asynchronously with q0-q6 while output en- able (oe#) is asserted low. ry/by#:ready/busy the ry/by# is a dedicated, open-drain output pin that indicates whether an automatic erase/program algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# or ce#, whichever happens first, in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to vcc. if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the de- vice is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 7 shows the outputs for ry/by# during write op- eration. q6:toggle bit i toggle bit i on q6 indicates whether an automatic pro- gram or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# or ce#, whichever happens first, in the command sequence (prior to the program or erase operation), and during the sector time- out. during an automatic program or erase algorithm opera- tion, successive read cycles to any address cause q6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, q6 stops toggling. after an erase command sequence is written, if all sec- tors selected for erasing are protected, q6 toggles and returns to reading array data. if not all selected sectors are protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
15 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 q2:toggle bit ii the "toggle bit ii" on q2, when used with q6, indicates whether a particular sector is actively erasing (that is, the automatic erase alorithm is in process), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# or ce#, whichever happens first, in the command sequence. q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. q6, by com- parison, indicates whether the device is actively eras- ing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sectors and mode information. refer to table 7 to compare outputs for q2 and q6. reading toggle bits q6/ q2 whenever the system initially begins reading toggle bit status, it must read q7-q0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on q7-q0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of q5 is high (see the section on q5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as q5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase op- eration. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that system initially determines that the toggle bit is toggling and q5 has not gone high. the system may continue to monitor the toggle bit and q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. alterna- tively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. q5 exceeded timing limits q5 will indicate if the program or erase time has ex- ceeded the specified limits (internal pulse count). under these conditions q5 will produce a "1". this time-out condition indicates that the program or erase cycle was not successfully completed. data# polling and toggle bit are the only operating functions of the device under this condition. if this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still func- tional and may be used for the program or erase opera- tion. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. the system can use q6 and q2 together to determine whether a sector is actively erasing or is erase sus- pended. when the device is actively erasing (that is, the automatic erase algorithm is in progress), q6 toggling. when the device enters the erase suspend mode, q6 stops toggling. however, the system must also use q2 to determine which sectors are erasing or erase-sus- pended. alternatively, the system can use q7. if a program address falls within a protected sector, q6 toggles for approximately 2 us after the program com- mand sequence is written, then returns to reading array data. q6 also toggles during the erase-suspend-program mode, and stops toggling once the automatic program algo- rithm is complete. table 7 shows the outputs for toggle bit i on q6.
16 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 q3 sector erase timer after the completion of the initial sector erase command sequence, the sector erase time-out will begin. q3 will remain low until the time-out is complete. data# polling and toggle bit are valid after the initial sector erase com- mand sequence. if data# polling or the toggle bit indicates the device has been written with a valid erase command, q3 may be used to determine if the sector erase timer window is still open. if q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data# polling or toggle bit. if q3 is low ("0"), the device will accept additional sector erase commands. to insure the com- mand has been accepted, the system software should check the status of q3 prior to and following each sub- sequent sector erase command. if q3 were high on the second status check, the command may not have been accepted. data protection the kh29lv400c t/b is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically re- sets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down tran- sition or system noise. write pulse "glitch" protection noise pulses of less than 5ns(typical) on ce# or we# will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe# = vil, ce# = vih or we# = vih. to initiate a write cycle ce# and we# must be a logical zero while oe# is a logical one. pow er supply decoupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected be- tween its vcc and gnd. power-up sequence the kh29lv400c t/b powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of the predefined command sequences. temporary sector unprotect this feature allows temporary unprotection of previously protected sector to change data in-system. the tempo- rary sector unprotect mode is activated by setting the reset# pin to vid(11.5v-12.5v). during this mode, for- merly protected sectors can be programmed or erased as un-protected sector. once vid is remove from the reset# pin, all the previously protected sectors are pro- tected again. sector protection the kh29lv400c t/b features hardware sector protec- tion. this feature will disable both program and erase operations for these sectors protected. to activate this mode, the programming equipment must force vid on address pin a9 and oe# (suggest vid = 12v). program- ming of the protection circuitry begins on the falling edge of the we# pulse and is terminated on the rising edge. please refer to sector protect algorithm and waveform. if this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- taining that byte is bad and this sector maynot be re- used, (other sectors are still functional and can be re- used). the time-out condition will not appear if a user tries to program a non blank location without erasing. please note that this is not a device failure condition since the device was incorrectly used.
17 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 chip unprotect the kh29lv400c t/b also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. it is recommended to protect all sectors before activating chip unprotect mode. to activate this mode, the programming equipment must force vid on control pin oe# and address pin a9. the ce# pins must be set at vil. pins a6 must be set to vih.(see table 2) refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. the unprotection mechanism begins on the falling edge of the we# pulse and is terminated on the rising edge. it is also possible to determine if the chip is unprotected in the system by writing the read silicon id command. performing a read operation with a1=vih, it will produce 00h at data outputs(q0-q7) for an unprotected sector. it is noted that all sectors are unprotected after the chip unprotect algorithm is completed. to verify programming of the protection circuitry, the pro- gramming equipment must force vid on address pin a9 ( with ce# and oe# at vil and we# at vih). when a1=vih, a0=vil, a6=vil, it will produce a logical "1" code at device output q0 for a protected sector. other- wise the device will produce 00h for the unprotected sec- tor. in this mode, the addresses, except for a1, are don't care. address locations with a1 = vil are reserved to read manufacturer and device codes. (read silicon id) it is also possible to determine if the sector is protected in the system by writing a read silicon id command. performing a read operation with a1=vih, it will produce a logical "1" at q0 for the protected sector.
18 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . ..... -65 o c to +150 o c ambient temperature with power applied. . . . . . . . . . . . . .... -65 o c to +125 o c voltage with respect to ground vcc (note 1) . . . . . . . . . . . . . . . . . -0.5 v to +4.0 v a9, oe#, and reset# (note 2) . . . . . . . . . . . ....-0.5 v to +12.5 v all other pins (note 1) . . . . . . . -0.5 v to vcc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may over- shoot vss to -2.0 v for periods of up to 20 ns. maxi- mum dc voltage on input or i/o pins is vcc +0.5 v. during voltage transitions, input or i/o pins may over- shoot to vcc +2.0 v for periods up to 20 ns. 2. minimum dc input voltage on pins a9, oe#, and re- set# is -0.5 v. during voltage transitions, a9, oe#, and reset# may overshoot vss to -2.0 v for periods of up to 20 ns. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. operating ratings commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0 c to +70 c v cc supply voltages v cc for full voltage range. . . . . . . . . . . +2.7 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed.
19 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 table 8. capacitance ta = 25 o c, f = 1.0 mhz symbol p arameter min. typ max. unit conditions cin1 input capacitance 8 pf vin = 0v cin2 control pin capacitance 12 pf vin = 0v cout output capacitance 12 pf vout = 0v notes: 1. vil min. = -1.0v for pulse width is equal to or less than 50 ns. vil min. = -2.0v for pulse width is equal to or less than 20 ns. 2. vih max. = vcc + 1.5v for pulse width is equal to or less than 20 ns if vih is over the specified maximum value, read operation cannot be guaranteed. 3. automatic sleep mode enable the low power mode when addresses remain stable for tacc +30ns. 4. vih min.=0.7xvcc. the vih min. voltage is less than 2.4v. symbol p arameter min. typ max. unit conditions ili input leakage current 1 ua vin = vss to vcc ilit a9 input leakage current 35 ua vcc=vcc max; a9=12.5v ilo output leakage current 1 ua vout = vss to vcc, vcc=vcc max icc1 vcc active read current 7 12 ma ce#=vil, oe#=vih @5mhz 2 4 ma (byte mode) @1mhz 7 12 ma ce#=vil, oe#=vih @5mhz 2 4 ma (word mode) @1mhz icc2 vcc active write currect 15 30 ma ce#=vil, oe#=vih icc3 vcc standby currect 0.2 5 ua ce#; reset#=vcc 0.3v icc4 vcc standby currect 0.2 5 ua reset#=vss 0.3v during reset icc5 automatic sleep mode 0.2 5 ua vih=vcc 0.3v;vil=vss 0.3v vil input low voltage(note 1) -0.5 0.8 v vih input high voltage 0.7xvcc vcc+ 0.3 v (note 4) vid voltage for automative select and temporary 11.5 12.5 v vcc=3.3v chip unprotect vol output low voltage 0.45 v iol = 4.0ma, vcc= vcc min voh1 output high voltage(ttl) 0.85xvcc ioh = -2ma, vcc=vcc min voh2 output high voltage vcc-0.4 ioh = -100ua, vcc min (cmos) table 9. dc characteristics
20 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 29l v400c-70 29l v400c-90 symbol p arameter min. max. min. max. unit conditions trc read cycle time (note 1) 70 90 ns tacc address to output delay 70 90 ns ce#=oe#=vil tce ce# to output delay 70 90 ns oe#=vil toe oe# to output delay 30 35 ns ce#=vil tdf oe# high to output float (note 2) 0 25 0 30 ns ce#=vil toeh output enable read 0 0 ns hold time toggle and 10 10 ns data# polling toh address to output hold 0 0 ns ce#=oe#=vil notes : 1. not 100% tested. 2. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven. test conditions: input pulse levels: 0v/3.0v. input rise and fall times is equal to or less than 5ns. output load: 1 ttl gate + 100pf (including scope and jig), for 29lv400ct/b-90. 1 ttl gate + 30pf (including scope and jig) for 29lv400ct/b-70. reference levels for measuring timing: 1.5v. ac characteristics table 10. read operations
21 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 1. switching test circuits figure 2. switching test waveforms test points 3.0v 0v ac testing: inputs are driven at 3.0v for a logic "1" and 0v for a logic "0". input pulse rise and fall times are < 5ns. output 1.5v 1.5v input device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=100pf including jig capacitance cl=30pf for kh29lv400c t/b-70
22 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 3. read timing waveforms addresses ce# oe# tacc we# vih vil vih vil vih vil vih vil voh vol vih vil high z high z data valid toe toeh tdf tce tacc trc outputs reset# toh add valid
23 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 parameter speed options std. description 70 90 unit twc write cycle time (note 1) min 70 90 ns tas address setup time min 0 ns tah address hold time min 45 ns tds data setup time min 35 45 ns tdh data hold time min 0 ns toes output enable setup time min 0 ns tghwl read recovery time before write min 0 ns (oe# high to we# low) tcs ce# setup time min 0 ns tch ce# hold time min 0 ns twp write pulse width min 35 ns twph write pulse width high min 30 ns twhwh1 programming operation (note 2) typ 9/11 us (byte/word program time) twhwh2 sector erase operation (note 2) typ 0.7 sec tvcs vcc setup time (note 1) min 50 us trb recovery time from ry/by# min 0 ns tbusy program/erase vaild to ry/by# delay max 90 ns twpp1 write pulse width for sector protect min 100 ns (a9, oe# control) typ 10 us twpp2 write pulse width for sector unprotect min 100 ns (a9, oe# control) typ 12 ms tbal sector address load time max 50 us notes: 1. not 100% tested. 2. see the "erase and programming performance" section for more information. ac characteristics table 11. erase/program operations
24 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 parameter speed options std. description 70 90 unit twc write cycle time (note 1) min 70 90 ns tas address setup time min 0 ns tah address hold time min 45 ns tds data setup time min 35 45 ns tdh data hold time min 0 ns toes output enable setup time min 0 ns tghel read recovery time before write min 0 ns tws we# setup time min 0 ns twh we# hold time min 0 ns tcp ce# pulse width min 35 ns tcph ce# pulse width high min 30 ns twhwh1 progr amming byte typ 9 us operation (note2) word typ 11 us twhwh2 sector erase operation (note2) typ 0.7 sec note: 1. not 100% tested. 2. see the "erase and programming performance" section for more information. ac characteristics table 12. alternate ce# controlled erase/program operations
25 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 4. command write timing waveform addresses ce# oe# we# din tds tah data tdh tcs tch tcwc twph twp toes tas vcc 3v vih vil vih vil vih vil vih vil vih vil add valid
26 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 automatic programming timing waveform figure 5. automatic programming timing waveform one byte data is programmed. verify in fast algorithm and additional verification by external control are not re- quired because these operations are executed automati- cally by internal control circuit. programming comple- tion can be verified by data# polling and toggle bit check- ing after automatic programming starts. device outputs data# during programming and data# after programming on q7.(q6 is for toggle bit; see toggle bit, data# polling, timing waveform) twc address oe# ce# a0h 555h pa pd status dout pa pa notes: 1.pa=program address, pd=program data, dout is the true data the program address tas tah tghwl tch twp tds tdh twhwh1 read status data (last two cycle) program command sequence(last two cycle) tbusy trb tcs twph tvcs we# data ry/by# vcc
27 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 6. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes verify word ok ? yes auto program completed data poll from system increment address last address ? no no
28 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 7. ce# controlled program timing waveform twc twh tghel twhwh1 or 2 tcp address we# oe# ce# data q7 pa data# polling dout reset# ry/by# notes: 1.pa=program address, pd=program data, dout=data out, q7=complement of data written to device. 2.figure indicates the last two bus cycles of the command sequence. tah tas pa for program sa for sector erase 555 for chip erase trh tdh tds tws a0 for program 55 for erase tcph tbusy pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase
29 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 all data in chip are erased. external erase verification is not required because data is verified automatically by internal control circuit. erasure completion can be veri- fied by data# polling and toggle bit checking after auto- matic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data# polling, timing waveform) figure 8. automatic chip erase timing waveform automatic chip erase timing waveform twc address oe# ce# 55h 2aah 555h 10h in progress complete va va notes: sa=sector address(for sector erase), va=valid address for reading status data(see "write operation status"). tas tah tghwl tch twp tds tdh twhwh2 read status data erase command sequence(last two cycle) tbusy trb tcs twph tvcs we# data ry/by# vcc
30 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 9. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no data=ffh ? write data 10h address 555h write data 55h address 2aah data pall from system auto chip erase completed
31 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 10. automatic sector erase timing waveform sector indicated by a12 to a17 are erased. external erase verify is not required because data are verified automatically by internal control circuit. erasure comple- tion can be verified by data# polling and toggle bit check- ing after automatic erase starts. device outputs 0 dur- ing erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data# polling, timing waveform) automatic sector erase timing waveform twc address oe# ce# 55h 2aah sector address 1 sector address 0 30h in progress complete va va 30h notes: sa=sector address(for sector erase), va=valid address for reading status data(see "write operation status"). sector address n tas tah tbal tghwl tch twp tds tdh twhwh2 read status data erase command sequence(last two cycle) tbusy trb tcs twph tvcs we# data ry/by# vcc 30h
32 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 11. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah data poll from system auto sector erase completed no last sector to erase yes yes no data=ffh
33 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 12. erase suspend/erase resume flowchart note: if the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times, then the 10ms time delay must be put into consideration. start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h delay 10ms (note) continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume
34 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 13. in-system sector protect/unprotect timing waveform (reset# control) sector protect =150us sector unprotect =15ms 1us vid vih data sa, a6 a1, a0 ce# we# oe# valid* valid* status valid* sector protect or sector unprotect 40h 60h 60h verify reset# note: when sector protect, a6=0, a1=1, a0=0. when sector unprotect, a6=1, a1=1, a0=0.
35 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 14. sector protect timing waveform (a9, oe# control) toe data oe# we# 12v 3v 12v 3v ce# a9 a1 a6 toesp twpp 1 tvlht tvlht tvlht verify 01h f0h a18-a12 sector address
36 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 15. sector protection algorithm (a9, oe# control) start set up sector addr plscnt=1 sector protection complete data=01h? ye s oe#=vid, a9=vid, ce#=vil a6=vil activate we# pulse time out 150us set we#=vih, ce#=oe#=vil a9 should remain vid read from sector addr=sa, a1=1 protect another sector? remove vid from a9 write reset command device failed plscnt=32? ye s no no
37 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 16. in-system sector protection algorithm with reset#=vid start plscnt=1 first write cycle=60h ye s no reset#=vid wait 1us set up sector address write 60h to sector address with a6=0, a1=1, a0=0 verify sector protect : write 40h with a6=0, a1=1, a0=0 wait 150us increment plscnt read from sector address remove vid from reset# temporary sector unprotect mode reset plscnt=1 data=01h ye s ye s ye s no no no ? plscnt=25? protect another sector? write reset command sector protect complete device failed
38 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 17. in-system sector unprotection algorithm with reset#=vid start plscnt=1 first write cycle=60h ? ye s no reset#=vid wait 1us set up first sector address chip unprotect : write 60h with a6=1, a1=1, a0=0 verify chip unprotect write 40h to sector address with a6=1, a1=1, a0=0 wait 50ms increment plscnt read from sector address with a6=1, a1=1, a0=0 remove vid from reset# temporary sector unprotect mode set up next sector address all sector protected? ye s data=00h ye s ye s ye s no no no no protect all sectors ? plscnt=1000? last sector verified? write reset command chip unprotect complete device failed
39 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 18. timing waveform for chip unprotection (a9, oe# control) notes: twpp1 (write pulse width for sector protect)=100ns min, 10us(typ.) twpp2 (write pulse width for sector unprotect)=100ns min, 12ms(typ.) toe data oe# we# 12v 3v 12v 3v ce# a9 a1 toesp twpp 2 tvlht tvlht tvlht verify 00h a6 sector address a18-a12 f0h
40 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 19. chip unprotection algorithm (a9, oe# control) start protect all sectors plscnt=1 chip unprotect complete data=00h? ye s set oe#=a9=vid ce#=vil, a6=1 activate we# pulse time out 50ms set oe#=ce#=vil a9=vid,a1=1 set up first sector addr all sectors have been verified? remove vid from a9 write reset command device failed plscnt=1000? no increment plscnt no read data from device ye s ye s no increment sector addr * it is recommended before unprotect whole chip, all sectors should be protected in advance.
41 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 20. data# polling algorithm write operation status read q7~q0 add.=va(1) read q7~q0 add.=va start q7 = data ? q5 = 1 ? q7 = data ? fail pass no no (2) no ye s ye s ye s note : 1.va=valid address for programming 2.q7 should be re-checked even q5="1" because q7 may change simultaneously with q5.
42 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 21. toggle bit algorithm read q7-q0 read q7-q0 q5= 1? read q7~q0 twice program/erase operation not complete,write reset command program/erase operation complete toggle bit q6= toggle? toggle bit q6 = toggle ? no (note 1) (note 1,2) yes no no yes yes note:1.read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 change to "1". start
43 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 22. data# polling timings (during automatic algorithms) ry/by# notes: 1. va=valid address. figure shows are first status cycle after command sequence, last status read cycle, and array data read cy cle. tdf tce tacc trc tch toe toeh toh tbusy address ce# oe# we# q7 q0-q6 status data status data complement complement valid data tr u e va va va high z high z valid data tr u e
44 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 23. toggle bit timing waveforms (during automatic algorithms) notes: 1. va=valid address; not required for q6. figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. tdf tce tacc trc tch toe toeh tbusy high z toh address ce# oe# we# q6/q2 ry/by# valid status (first read) valid status (second read) (stops toggling) valid data va va va va valid data
45 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 24. reset# timing waveform table 13. ac characteristics parameter std description test setup all speed options unit tready1 reset# pin low (during automatic algorithms) max 20 us to read or write (see note) tready2 reset# pin low (not during auto matic max 500 ns algorithms) to read or write (see note) trp reset# pulse width (during automatic algorithms) min 500 ns trh reset# high time before read(see note) min 50 ns trb ry/by# recovery time(to ce#, oe# go low) min 0 ns note:not 100% tested trh trb tready1 trp trp tready2 ry/by# ce#, oe# reset# reset timing not during automatic algorithms reset timing during automatic algorithms ry/by# ce#, oe# reset#
46 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 25. byte# timing waveform for read operations (byte# switching from byte mode to word mode) ac characteristics word/byte configuration (byte#) parameter description speed options unit jedec std -70 -90 telfl/telfh ce# to byte# switching low or high max 5 ns tflqz byte# switching low to output high z max 25 30 ns tfhqv b yte# switching high to output active min 70 90 ns tfhqv telfh dout (q0-q7) dout (q0-q14) va dout (q15) ce# oe# byte# q0~q14 q15/a-1
47 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 26. byte# timing waveform for read operations (byte# switching from word mode to byte mode) figure 27. byte# timing waveform for program operations tas tah the falling edge of the last we# signal ce# we# byte# tflqz telfh dout (q0-q7) dout (q0-q14) va dout (q15) ce# oe# byte# q0~q14 q15/a-1
48 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 table 14. temporary sector unprotect parameter std. description test setup all speed options unit tvidr vid rise and fall time (see note) min 500 ns trsp reset# setup time for temporary sector unprotect min 4 us note: not 100% tested figure 28. temporary sector unprotect timing diagram figure 29. q6 vs q2 for erase and erase suspend operations reset# ce# we# ry/by# tvidr tvidr program or erase command sequence 12v 0 or vcc 0 or vcc trsp notes: the system can use oe# or ce# to toggle q2/q6, q2 toggles only when read at an address within an erase-suspended we# enter embedded erasing erase suspend enter erase suspend program erase suspend program erase suspend read erase erase resume erase complete erase q6 q2
49 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 30. temporary sector unprotect algorithm start reset# = vid (note 1) perform erase or program operation reset# = vih temporary sector unprotect completed(note 2) note : 1. all protected sectors are temporary unprotected. vid=11.5v~12.5v 2. all previously protected sectors are protected again. operation completed
50 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 figure 31. id code read timing waveform tacc tce tacc toe toh toh tdf data out c2h/00c2h b9h/bah (byte) 22b9h/22bah (word) vid vih vil add a9 add a2-a8 a10-a17 ce# oe# we# add a0 data out data q0-q15 vcc a1 3v vih vil vih vil vih vil vih vil vih vil vih vil vih vil
51 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a. ac timing at device power-up notes : 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v tr input signal rise time 1,2 20 us/v tf input signal fall time 1,2 20 us/v vcc address ce# we# oe# data tvr tacc tr or tf tce tf vcc(min) gnd vih vil vih vil vih vil vih vil voh high z vol wp#/acc vih vil valid ouput valid address tr or tf tr toe tf tr
52 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 12.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. limits parameter min. typ.(2) max.(3) units sector erase time 0.7 15 sec chip erase time 4 32 sec byte programming time 9 300 us word programming time 11 360 us chip programming time byte mode 4.5 13.5 sec word mode 3 9 sec erase/program cycles 100,000 cycles table 16. latch-up characteristics table 15. erase and programming performance (1) note: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25 c, 3v. 3.maximum values measured at 25 c, 2.7v. table 17. data retention parameter description test conditions min unit 150 c 10 years data retention time 125 c 20 years
53 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 query command and common flash interface (cfi) mode ( for kh29lv400ct/ cb) kh29lv400ct/cb is capable of operating in the cfi mode. this mode all the host system to determine the manufacturer of the device such as operating param- eters and configuration. two commands are required in cfi mode. query command of cfi mode is placed first, then the reset command exits cfi mode. these are table 18-1. cfi mode: identification data values (all values in these tables are in hexadecimal) description address address data (byte mode) (word mode) query-unique ascii string "qry" 20 10 0051 22 11 0052 24 12 0059 primary vendor command set and control interface id code 26 13 0002 28 14 0000 address for primary algorithm extended query table 2a 15 0040 2c 16 0000 alternate vendor command set and control interface id code (none) 2e 17 0000 30 18 0000 address for secondary algorithm extended query table (none) 32 19 0000 34 1a 0000 table 18-2. cfi mode: system interface data values (all values in these tables are in hexadecimal) description address address data (byte mode) (word mode) vcc supply, minimum (2.7v) 36 1b 0027 vcc supply, maximum (3.6v) 38 1c 0036 vpp supply, minimum (none) 3a 1d 0000 vpp supply, maximum (none) 3c 1e 0000 typical timeout for single word/byte write (2 n us) 3e 1f 0004 typical timeout for minimum size buffer write (2 n us) 40 20 0000 typical timeout for individual block erase (2 n ms) 42 21 000a typical timeout for full chip erase (2 n ms) 44 22 0000 maximum timeout for single word/byte write times (2 n x typ) 46 23 0005 maximum timeout for buffer write times (2 n x typ) 48 24 0000 maximum timeout for individual block erase times (2 n x typ) 4a 25 0004 maximum timeout for full chip erase times (not supported) 4c 26 0000 described in table 18. the single cycle query command is valid only when the device is in the read mode, including erase suspend, standby mode, and read id mode; however, it is ignored otherwise. the reset command exits from the cfi mode to the read mode, or erase suspend mode, or read id mode. the command is valid only when the device is in the cfi mode.
54 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 table 18-3. cfi mode: device geometry data values (all values in these tables are in hexadecimal) description address address data (byte mode) (word mode) device size (2 n bytes) 4e 27 0013 flash device interface code (refer to the cfi publication 100) 50 28 0002 52 29 0000 maximum number of bytes in multi-byte write (not supported) 54 2a 0000 56 2b 0000 number of erase block regions 58 2c 0004 erase block region 1 information (refer to the cfi publication 100) 5a 2d 0000 5c 2e 0000 5e 2f 0040 60 30 0000 erase block region 2 information 62 31 0001 64 32 0000 66 33 0020 68 34 0000 erase block region 3 information 6a 35 0000 6c 36 0000 6e 37 0080 70 38 0000 erase block region 4 information 72 39 0006 74 3a 0000 76 3b 0000 78 3c 0001 table 18-4. cfi mode: primary vendor-specific extended query data values (all values in these tables are in hexadecimal) description address address data (byte mode) (word mode) query-unique ascii string "pri" 80 40 0050 82 41 0052 84 42 0049 major version number, ascii 86 43 0031 minor version number, ascii 88 44 0030 address sensitive unlock (0=required, 1= not required) 8a 45 0000 erase suspend (2= to read and write) 8c 46 0002 sector protect (n= # of sectors/group) 8e 47 0001 temporary sector unprotected (1=supported) 90 48 0001 sector protect/unprotected scheme 92 49 0004 simultaneous r/w operation (0=not supported) 94 4a 0000 burst mode type (0=not supported) 96 4b 0000 page mode type (0=not supported) 98 4c 0000
55 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 ordering information part no. access operating standby package remark time (ns) current max. (ma) current max. (ua) kh29lv400cttc-70 70 30 5 48 pin tsop (normal type) KH29LV400CBtc-70 70 30 5 48 pin tsop (normal type) kh29lv400cttc-90 90 30 5 48 pin tsop (normal type) KH29LV400CBtc-90 90 30 5 48 pin tsop (normal type) kh29lv400cttc-70g 70 30 5 48 pin tsop pb free (normal type) KH29LV400CBtc-70g 70 30 5 48 pin tsop pb free (normal type) kh29lv400cttc-90g 90 30 5 48 pin tsop pb free (normal type) KH29LV400CBtc-90g 90 30 5 48 pin tsop pb free (normal type)
56 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 part name description kh 29 lv 70 c t t c g option: g: lead-free package blank: normal speed: 70: 70ns 90: 90ns temperature range: c: commercial (0?c to 70?c) package: t: tsop boot block type: t: top boot b: bottom boot revision: c density & mode: 400: 4m, x8/x16 boot block type: l, lv: 3v device: 29:flash 400
57 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 package information
58 p/n:pm1219 kh29lv400c t/b rev. 1.3, dec. 09, 2005 revision history revision no. description page date 1.1 1. modified "package information" p57 jul/01/2005 1.2 1. modified "low power consumption--active current" from 20ma(max.) p1 a ug/30/2005 to 30ma(max.) 2. added description about pb-free devices are rohs compliant p1 1.3 1. modified content error p44,45,51 dec/09/2005
kh29lv400c t/b m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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